1. Field of the Invention
The present invention relates to a display, and more specifically, it relates to an active matrix display having a switching element every pixel.
2. Description of the Prior Art
Displays are roughly classified into a passive matrix display and an active matrix display in general. The active matrix display is provided with a switching element for each pixel, for applying a voltage (or feeding a current) responsive to image data to each pixel thereby making display.
A liquid crystal display (LCD) sealing liquid crystals between opposite substrates applies a voltage to a pixel electrode formed every pixel for varying transmittance for the liquid crystals thereby making display. An active matrix LCD having a high image quality forms the mainstream particularly in application to a monitor.
An electroluminescence (EL) display feeds a current to an EL element from a pixel electrode formed every pixel thereby making display. Active study is made in order to put an active matrix EL display into practice.
Particularly in the so-called low-temperature polysilicon TFT (thin-film transistor) obtained by fabricating a semiconductor layer of a thin-film transistor applied to a switching element without through a high-temperature process, various types of peripheral circuits can be integrally formed on a glass substrate. Therefore, no driving IC may be connected to the periphery, and hence the cost can be reduced. The low-temperature polysilicon TFT can be applied to various active matrix displays such as a plasma display, a field emission display (FED) and an electrophoretic display, in addition to the aforementioned LCD and the aforementioned EL display.
FIG. 13 is a conceptual diagram showing a conventional active matrix LCD. Referring to FIG. 13, an external control circuit 200 is connected to an LCD panel 100 prepared by arranging various types of circuits on a glass substrate in the conventional active matrix LCD.
The external control circuit 200 supplies various control signals, video signals, a power supply voltage VDD etc. to the LCD panel 100, in order to drive the LCD panel 100. The external control circuit 200 formed by a general CMOS circuit operates at a low voltage of 3 V, for example, and outputs control signals of 3 V in amplitude.
A display area 10 and various circuits are arranged on the LCD panel 100. A plurality of pixel electrodes 9 arranged in the form of a matrix, a plurality of signal lines 6 extending in a column direction and a plurality of scanning lines 7 extending in a row direction are arranged on the display area 10. Selection transistors 8 are arranged on the respective intersections between the signal lines 6 and the scanning lines 7. The selection transistors 8 have drain or source electrodes connected to the signal lines 6, gate electrodes connected to the scanning lines 7 and sources connected to the pixel electrodes 9. A primary color filter (not shown) of red, green or blue is arranged in correspondence to each pixel electrode 9, for making color display.
A signal line driving circuit 21 and a scanning line driving circuit 22 are arranged on a column side and a row side of the display area 10 respectively. A step-up circuit 40 is connected between the signal line and scanning line driving circuits 21 and 22 and the external control circuit 200. The step-up circuit 40 is formed by level shifters 41 for increasing voltage levels and buffers 42 improving current drivability. These level shifters 41 and buffers 42 are arranged for control signals to be stepped up respectively. The signal line driving circuit 21 and the scanning line driving circuit 22 are formed by shift registers.
FIG. 14 is a circuit diagram showing the signal line driving circuit 21 and a level shifter group of the conventional active matrix display. Referring to FIG. 14, the signal line driving circuit 21 includes a shift register 23 and a plurality of RGB selection circuits 24 (24a, 24b, 24c, . . . ). The shift register 23 is formed by a plurality of latch circuits 25 (25a, 25b, 25c, . . . ). A horizontal clock HCK supplied from the external control circuit 200 is input in the latch circuits 25 of the respective stages. The RGB selection circuits 24 are formed by triple signal line selection transistors 26 (26Ra, 26Ga and 26Ba, 26Rb, 26Gb and 26Bb, . . . ) having gates connected with outputs of the latch circuits 25. The signal line selection transistors 26 have drains connected to any of video signal lines 300R, 300G and 300B and sources connected to the signal lines 6 (6Ra, 6Ga and 6Ba, 6Rb, 6Gb and 6Bb, 6Rc, 6Gc and 6Bc, . . . ).
Operations of the conventional active matrix display are now described with reference to FIGS. 13 and 14. Referring to FIG. 13, the scanning line driving circuit 22 sequentially selects prescribed scanning lines 7 from the plurality of scanning lines 7 and applies a gate voltage VG thereto, thereby turning on the selection transistors 8 connected to the scanning lines 7. The scanning line driving circuit 22 selects the first scanning line 7 with vertical start signal VST, while sequentially switching to and selecting subsequent scanning lines 7 in response to a vertical clock VCK.
The signal line driving circuit 21 selects a prescribed signal line 6 from the plurality of signal lines 6 and supplies RGB video signals to the pixel electrodes 9 through the signal line 6 and the selection transistor 8. The signal line driving circuit 21 selects one or a plurality of signal lines 6 at once. The signal line driving circuit 21 selects the first signal line 6 with a horizontal start signal HST, while sequentially switching to and selecting subsequent signal lines 6 in response to the horizontal clock HCK.
The step-up circuit 40 steps up low-voltage clocks VCKL and HCKL of 3 V in amplitude output from the external control circuit 200 to 12 V, for example, thereby generating the aforementioned vertical clock VCK and the aforementioned horizontal clock HCK. Each signal line 6 or each scanning line 7 connected with a large number of pixel electrodes 9 cannot be driven with a low voltage of about 3 V. Therefore, the step-up circuit 40 steps up control signals supplied from the external control circuit 200 to high voltages of 12 V.
Referring to FIG. 14, the horizontal start signal HST is input in the first-stage latch circuit 25a. An output of the latch circuit 25a receiving the horizontal start signal HST goes high for a period of the cycle of the horizontal clock HCK responsive to the pulse width of the horizontal start signal HST. The signal line selection transistors 26Ra, 26Ga and 26Ba enter ON states due to the output of the latch circuit 25a respectively. Thus, video signals are supplied to the signal lines 6Ra, 6Ga and 6Ba from the video signal lines 300R, 300G and 300B respectively. The output of the first-stage latch circuit 25a is input in the second-stage latch circuit 25b. An output of the latch circuit 25b shifts from the output of the latch circuit 25a by half the cycle of the horizontal clock HCK and goes high for a desired period. Thus, the video signals are supplied to the signal lines 6Rb, 6Gb and 6Bb from the video signal lines 300R, 300G and 300G. Thereafter outputs of the subsequent latch circuits 25 sequentially go high for sequentially selecting the corresponding signal lines 6 and supplying the video signals to all pixels.
When all signal lines 6 of one row are selected, the vertical clock VCK enters a next cycle and the scanning line driving circuit 22 supplies the gate voltage VG to the subsequent scanning line 7. The horizontal start signal HST is input again so that the output of the first-stage latch circuit 25a goes high.
Recently, requirement for reduction of power consumption for a display is increased following popularization of a portable telephone and a portable information terminal.
In the aforementioned prior art, however, the horizontal clock HCK and the vertical clock VCK are supplied to the shift registers 23 of all stages of the signal line driving circuit 21 and the scanning line driving circuit 22 for driving the same. Therefore, the conventional active matrix display requires large current drivability. Consequently, power consumption is disadvantageously inevitably increased. In particular, the buffers 42 of the step-up circuit 40 for ensuring high current drivability require large power consumption.
In order to solve this problem, a plurality of level shifters connected to at least either the signal line driving circuit 21 or the scanning line driving circuit 22 may be driven in a time-divisional manner. In this case, however, an operation failure may be readily caused when a signal is delayed, for example.